Extremely high density packaging of microelectronic circuits is useful not only in saving space, but also in reducing signal path length to increase the speed of the circuit, particularly in the construction of very large and high speed computers. One technique which has been developed to provide extremely high density packaging, described in U.S. Pat. No. 3,917,983, utilizes stacks of wafers to mount and interconnect a large number of miniature integrated circuit devices, in a three-dimensional arrangement that minimizes the average signal path length between the devices. This technique utilizes several component-mount wafers in each stack that each support and connect to several micro-circuit devices, and several intermediate connection wafers disposed between the component mount wafers to provide interconnect signal paths in the X, Y, and Z directions.
Although a device packaged in accordance with the aforecited U.S. Pat. No. 3,917,983 has inherently good heat dissipation characteristics attributable primarily to the use of metal wafers, nevertheless as packaging densities increase, heat dissipation can become an important problem. A stack with perhaps nine levels of circuit devices may have an external heat-dissipating area of perhaps only twice that of a single level, so that air blowers cannot easily dissipate the heat. Furthermore, the dissipation of heat from circuit devices located at the middle of the stack can be difficult, and, of course, all of the circuit devices must be cooled below a performance-degrading temperature regardless of general heat dissipation from the entire stack. A cooling apparatus which could efficiently dissipate large quantities of heat from a stack containing heat-generating circuit devices at multiple levels therein, to cool even those circuit devices at the center of the stack to a moderate temperature, would be of considerable aid in the design of very high density circuits. It is also desirable that any such cooling apparatus itself be compact, so that a large number of stacks can be placed close together to minimize the spacing between adjacent stacks, to thereby minimize the time required for signals to pass between the stacks.